Present digital integrated circuits (ICs) contain millions and even billions of combinational and sequential logic gates, along with the necessary connections there between to operate in a desired manner. As a result, integrated circuit (IC) design has become a significantly laborious and complex process that involves several different steps.
Because of the large number of combinational and sequential logic gates, designers use a hardware description language (HDL) to specify the structure, design and operation of the circuit. HDLs are specialized computer languages that enable a precise, formal description of an electronic circuit that allows for the automated analysis, simulation, and simulated testing of the IC.
Once the HDL design is complete, a step called logic synthesis is performed by which an abstract form of desired circuit created by the HDL is turned into a design implementation in terms of logic gates, typically by a computer program called a synthesis tool. The output of a synthesis tool is called a netlist, which is a list of the combinational and sequential logic gates, and their connections, and is, in effect, the IC logic design that can be fabricated into an IC. Following logic synthesis, additional logic is inserted into the netlist to enable scan tests, which enable testing of manufactured ICs to determine IC detects. The basic concept of a scan test is to connect memory elements of the designed integrated circuit (e.g., flip flops or latches) forming chains, so that shifting test data through the scan chains enables the tester to observe the state of the manufactured IC.
FIG. 1 illustrates a conventional scan cell 100 that can be inserted into the netlist after synthesis. Scan cell 100 includes a multiplexer 110 with two inputs 112a, 112b, a selector input 114 to receive a “scan_enable” signal EN and an output 116 that is coupled to an input of flip flop 120. The multiplexer 110 is coupled to a flip flop 120 (i.e., a register or storage element of the IC). The flip flop 120 includes an input 122 and clock input 124 and an output 126. In this design, the first input 112a of the multiplexer 110 receives the functional data (often referred to as functional data signal (D)), the second input 112b receives scan-in data (often referred to as scan-in data signal (SI)), and the selector input 114 receives the selector input signal (often referred to as the scan_enable signal (SE)). If the selector signal is disabled or a low signal (i.e., a “0” digital signal input), the multiplexer 110 will pass the functional data signal (D) to the input 122 of the flip flop 120. In other words, during normal operation of the integrated circuit, the selector signal will be low, such that the flip flop is receiving the functional data. In contrast, if the scan_enable signal SE is enabled during a scan test, the scan-In data signal SI will be passed to the input 122 of the flip flop 120. Once these scan cells are created, the scan cells are connected into “scan chains,” which are usually accessed through test pins. FIG. 2 illustrates an example of shifting scan data through a conventional scan chain.
Even when a logically perfect IC design results from synthesis, the netlist corresponding to the HDL program may be less than optimal. One significant issue that can result from synthesis and scan chain insertion is the existence of unnecessary or redundant logic in the netlist. Redundant logic can be combinational or sequential logic gates in the IC's netlist that are unnecessary or irrelevant to the functionality of the IC. While a single redundant logic gate will have no bearing on the operation or size of the IC, a netlist for an IC containing millions or billions of logic gates might have a significant number of redundant logic gates, the removal of which would such would significantly decrease overall chip area once the IC is fabricated and provide significant flexibility to timing optimization of the IC.